PCIe

Note

Software support for PCIe connectivity will be made available in a future BSP release.

PCIe connectivity is accessible at the connector X20. The reference clock signals can be configured to sync with the clock generated externally by a PI6C557-03 PCI Express Clock generator at U1, or from the SERDES reference clock from the phyCORE-AM65x SOM. Reference the table below for the jumper settings available.

../_images/pcm-067-pcie-x20.png
Solder Jumper Configurations

J1-2

1+2

Sets the PCIe reference clock to the output of the U1 reference clock generator

2+3 (Default)

Sets the PCIe reference clock to the reference clock output from the phyCORE-AM65x SOM