Inline ECC

The DDR Subsystem (DDRSS) on the phyCORE-AM64x device includes the DDR controller, DDR PHY, and the associated wrapper logic that integrates these components. To ensure SDRAM data integrity, the DDRSS bridge implements inline Error Correction Code (ECC) functionality for both read and write operations.

ECC is stored inline with the data in SDRAM, eliminating the need for a separate ECC-specific memory device. The implemented ECC scheme uses an 8-bit Single Error Correction Double Error Detection (SECDED) code calculated over 64-bit data blocks. This results in 32 bytes of ECC for every 256 bytes of data, meaning 1/9th of the total SDRAM space is allocated for ECC, while the remaining 8/9th is available for actual data storage.

From the system’s perspective, memory addresses are presented as a continuous linear address space, regardless of whether the SDRAM region is ECC-protected or not. The 1/9th ECC overhead remains consistent across the memory.

Validating Inline ECC

U-Boot includes a custom ddrss command that allows users to verify the functionality of the inline ECC mechanism. This command can deliberately introduce bit-flips at specified memory addresses and subsequently check whether the ECC logic detects and corrects the errors as expected.

The example below demonstrates how to flip a single bit at memory address 0x82400000:

sh-uboot:~# ddrss ecc_err 82400000 1
Testing DDR ECC:
        ECC test: Disabling DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0, written data 0x1, err pattern: 0x1, read after write data 0x1
        ECC test: Enabled DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0
        ECC test: DDR ECC 1-bit error
        ECC test: 1-bit ECC err count: 1
        ECC test: 1-bit error in [0x2400000:0x2400008]

This command helps validate both error detection and correction capabilities of the DDRSS ECC feature.